In-line stacking of transistors for soft error rate hardening

A method of forming transistors, comprising:

• forming a first CMOS transistor in a first silicon island;
• forming a second CMOS transistor in a second silicon island, wherein the second silicon island is separate from the first silicon island and wherein the first and second silicon islands are arranged in an in-line configuration that reduces the probability of an ionizing radiation particle striking the first and second CMOS transistors causing a single event upset to occur;
• and
• providing a single gate terminal conductor for both the first and second CMOS transistors.

An integrated circuit, comprising:

• a first transistor located in a first semiconductor island;
• a second transistor located in a second semiconductor island, wherein the second semiconductor island is separate from the first semiconductor island and wherein the first and second semiconductor islands are arranged in an in-line configuration that reduces the probability of an ionizing radiation particle striking the first and second transistors causing a single event upset to occur;
• and
• a single gate terminal conductor for both the first and second transistors.

A method of forming transistors, comprising:

• forming a first CMOS transistor in a first silicon island using silicon-on-insulator technology;
• forming a second CMOS transistor in a second silicon island using silicon-on-insulator technology, wherein the second silicon island is separate from the first silicon island and wherein the first and second silicon islands are arranged in an in-line configuration that reduces the probability of an ionizing radiation particle striking the first and second CMOS transistors causing a single event upset to occur;
• and
• providing a single gate terminal conductor for both the first and second CMOS transistors.