US 2010/0301426 A1Published application

Depletion mos transistor and enhancement mos transistor

AssigneeKabushiki Kaisha Toshiba

InventorsHiroyuki KUTSUKAKE, Kenji GOMIKAWA, Yoshiko KATO, Mitsuhiro NOGUCHI, Masato ENDO

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

Claims18

Dependent claims

A semiconductor memory device comprising:

a memory cell array including a memory cell transistor with a charge layer formed on a semiconductor substrate with a gate insulating film interposed therebetween;
and
a peripheral circuit including at least a first transistor,
wherein the first transistor includes:
a first gate electrode disposed in a surface of a semiconductor layer with a first gate insulating film interposed therebetween;
a first channel region of a first conductivity type formed in the surface of the semiconductor layer close to a region located immediately below the first gate electrode, the first channel region having a first impurity concentration;
a first source region of the first conductivity type and a first drain region of the first conductivity type each formed in the surface of the semiconductor layer and each having a second impurity concentration higher than the first impurity concentration;
a first overlapping region of the first conductivity type formed in the surface of the semiconductor layer immediately below the first gate electrode where the first channel region overlaps the first source region and the first drain region, the first overlapping region having a third impurity concentration higher than the second impurity concentration;
a first contact region of the first conductivity type formed in at least a part of a surface of each of the first source region and the first drain region and having a fourth impurity concentration higher than the second impurity concentration;
and
a first impurity diffusion region of the first conductivity type formed in a partial region of one of the first source region and the first drain region and having a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration, and
the first impurity diffusion region is formed in contact with the first contact region and away from the first overlapping region and positioned at least in a region between the first contact region and the first overlapping region.

9 more elements

A depletion MOS transistor comprising:

a gate electrode disposed on a surface of a semiconductor layer with a gate insulating film interposed therebetween;
a channel region of a first conductivity type formed in the surface of the semiconductor layer close to a region located immediately below the gate electrode, the channel region having a first impurity concentration;
a source region of the first conductivity type and a drain region of the first conductivity type each formed in the surface of the semiconductor layer and each having a second impurity concentration higher than the first impurity concentration;
an overlapping region of the first conductivity type formed in the surface of the semiconductor layer immediately below the gate electrode where the channel region overlaps the source region and the drain region, the overlapping region having a third impurity concentration higher than the second impurity concentration;
a contact region of the first conductivity type formed in at least a part of a surface of each of the source region and the drain region and having a fourth impurity concentration higher than the second impurity concentration;
and
an impurity diffusion region of the first conductivity type formed in a partial region of one of the source region and the drain region and having a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration,
wherein the impurity diffusion region is formed in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/788,784Filed 27 May 2010
Priority: JP 2009-13132729 May 2009
Published: 2 Dec 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND
H10D 30/637
Insulated-gate field-effect transistors [IGFET]: lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on…