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US 2010/0301424 A1Published application
Nested and isolated transistors with reduced impedance difference
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsJohnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
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Abstract
A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
Claims18
A device comprising:
- a substrate;
- and
- a metal silicide contact stack on the substrate, wherein the metal silicide contact stack comprises at least first and second metal silicide contacts, the first metal silicide contact being over the second metal silicide contact.
A transistor comprising:
- a gate;
- and
- first and second contact regions on the substrate adjacent to the gate, wherein the first and second contact regions comprise metal silicide contact stacks, the metal silicide contact stack comprises at least first and second metal silicide contacts, the first metal silicide contact being over the second metal silicide contact.
An IC comprising:
- a substrate;
- a first metal silicide contact on the substrate;
- and
- a second metal silicide contact on the first metal silicide contact to form a metal silicide contact stack.
1 more element
Dependencies are inferred from the claim text.