Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode
AssigneeGlobalfoundries Inc.
InventorsStephan Kronholz, Markus Lenski, Vassilios Papageorgiou
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Abstract
Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.
Claims21
A method, comprising:
- forming a gate electrode structure above a semiconductor region, said gate electrode structure comprising a high-k dielectric material, a metal-containing cap layer formed above said high-k dielectric material, a semiconductor material formed above said metal-containing cap layer and a dielectric cap material formed above said semiconductor material, said gate electrode structure having a tapered bottom portion with a reduced length;
- forming a spacer on sidewalls of said gate electrode structure, said spacer having a first spacer portion adhering to said tapered bottom portion and having a second spacer portion adhering to a substantially non-tapered portion of said gate electrode structure;
- forming an embedded strain-inducing semiconductor material in said semiconductor region with a lateral offset determined by said first spacer portion;
- and
- forming drain and source regions of a transistor in at least a portion of said strain-inducing semiconductor alloy.
A method, comprising:
- forming a gate layer stack above a first semiconductor region and a second semiconductor region;
- patterning said gate layer stack to form a first gate electrode structure above said first semiconductor region and a second gate electrode structure above said second semiconductor region, said second gate electrode structure having greater effective gate length relative to said first gate electrode structure;
- forming a spacer layer above said first and second gate electrode structures, said spacer layer having a thickness of approximately 10 nm or less;
- forming a spacer element on sidewalls of said first gate electrode structure on the basis of said spacer layer;
- and
- forming a strain-inducing semiconductor alloy in said first semiconductor region by using said spacer element as a mask.
A semiconductor device, comprising:
- a gate electrode structure of a transistor formed above a semiconductor region and comprising an electrode material formed above a metal-containing cap material that is formed above a gate insulation layer comprising a high-k dielectric material, said gate electrode material having a bottom portion and a top portion of different length, a length of said bottom portion being approximately 50 nm or less;
- a strain-inducing semiconductor alloy formed in said semiconductor region;
- and
- drain and source regions at least partially formed in said strain-inducing semiconductor alloy.
Dependencies are inferred from the claim text.