Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions andan underlying floating well section

A static random access memory (SRAM) array structure comprising:

• a substrate having a first conductivity type;
• a well in said substrate, said well having a second conductivity type different from said first conductivity type;
• on said substrate above said well, a semiconductor layer comprising:
• a first source region for a first pull-up field effect transistor of a first memory cell;
• a second source region for a second pull-up field effect transistor for a second memory cell, said first source region and said second source region having said first conductivity type;
• and
• a doped region positioned laterally between said first source region and said second source region, said doped region having said second conductivity type and further extending vertically to said well;
• and
• a conductor layer on said semiconductor layer, said conductor layer extending laterally over and contacting said first source region, said doped region and said second source region.

A static random access memory (SRAM) array structure comprising:

• a P-substrate;
• an N+ well in said substrate;
• a semiconductor layer on said substrate;
• deep trench isolation regions extending through said semiconductor layer into said substrate to below said N+ well so as to define device regions of memory cells in said array, one of said device regions comprising:
• a section of said semiconductor layer above a section of said N+ well, said section of said semiconductor layer comprising:
• a first P-type source region for a first P-type pull-up field effect transistor of a first memory cell;
• a second P-type source region for a second P-type pull-up field effect transistor of a second memory cell adjacent to said first memory cell;
• and
• an N-type doped region positioned laterally between said first P-type source region and said second P-type source region, said N-type doped region further extending vertically to said section of said N+ well;
• a conductor layer on said semiconductor layer, said conductor layer extending laterally over and contacting said first P-type source region, said N-type doped region and said second P-type source region;
• and
• a contact on said conductor layer, said contact being connected to a positive supply voltage (Vdd).

A method of forming an integrated circuit device structure, said method comprising:

• providing a substrate having a first conductivity type;
• forming a well in said substrate, said well having a second conductivity type different from said first conductivity type;
• after said forming of said well, forming a semiconductor layer on said substrate;
• and
• forming a junction between said well, a first diffusion region of a first device and a second diffusion region of a second device, said forming of said junction comprising:
• forming, in said semiconductor layer, said first diffusion region and said second diffusion region such that said first diffusion region and said second diffusion region have said first conductivity type;
• forming, in said semiconductor layer, a third diffusion region positioned laterally between said first diffusion region and said second diffusion region such that said third diffusion region has said second conductivity type and extends vertically to said well;
• and
• forming a conductor layer on said semiconductor layer such that said conductor layer extends laterally over and contacts said first diffusion region, said third diffusion region and said second diffusion region.

A method of forming a static random access memory (SRAM) array structure, said method comprising:

• providing a a substrate having a first conductivity type;
• forming a well in said substrate, said well having a second conductivity type different from said first conductivity type;
• after said forming of said well, forming a semiconductor layer on said substrate;
• forming a junction between said well and a first source region of a first pull-up field effect transistor of a first memory cell and a second source region of a second pull-up field effect transistor of a second memory cell, said forming of said junction comprising:
• forming, in said semiconductor layer, said first source region for said first pull-up field effect transistor and said second source region for said second pull-up field effect transistor such that said first source region and said second source region have said first conductivity type;
• forming, in said semiconductor layer, a doped region positioned laterally between said first source region and said second source region such that said doped region has said second conductivity type and extends vertically to said well;
• and
• forming a conductor layer on said semiconductor layer such that said conductor layer extends laterally over and contacts said first source region, said doped region and said second source region.