Semiconductor device and production method thereof
AssigneeRenesas Electronics Corporation
InventorYoshiyuki KAWASHIMA
Life of this patent
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Abstract
An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.
Claims22
A semiconductor device comprising:
- a first memory cell and a second memory cell formed over the main face of a semiconductor substrate,
- wherein each of the first and second memory cells includes:
- a well of a first conductivity type formed in the semiconductor substrate;
- a first gate insulation film formed over the well;
- a control gate electrode formed over the semiconductor substrate through the first gate insulation film;
- a second gate insulation film extendedly formed over the sidewall on one side of the control gate electrode and the well;
- a memory gate electrode formed over the sidewall on one side of the control gate electrode and insulated from the control gate and electrode the semiconductor substrate through the second gate insulation film;
- a drain region comprised of a semiconductor region of a second conductivity type functioning as the conductivity type opposite to the first conductivity type formed over the semiconductor substrate in the vicinity of the control gate electrode;
- and
- a source region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the memory gate electrode, and
- wherein the gate length of the memory gate electrode of the first memory cell is longer than the gate length of the memory gate electrode of the second memory cell.
A method for producing a semiconductor device including a first memory cell having a first control gate electrode and a first memory gate electrode and a second memory cell having a second control gate electrode and a second memory gate electrode, the first and second memory cells being formed over the main face of a semiconductor substrate,
- the method comprising the steps of:
- (a) forming a well of a first conductivity type over the semiconductor substrate;
- (b) forming a first gate insulation film over the well;
- (c) forming the first and second control gate electrodes over the first gate insulation film;
- (d) after the step (c), forming a second gate insulation film over the main face of the semiconductor substrate;
- (e) after the step (d), forming a conductive film over the main face of the semiconductor substrate;
- (f) after the step (e), forming a first insulation film over the main face of the semiconductor substrate;
- (g) patterning the first insulation film in the manner of covering the first control gate electrode and the vicinity thereof;
- (h) after the step (g), forming a sidewall comprised of the first insulation film by anisotropic etching over the side face of the conductive film with which the sidewall of the first control gate electrode is covered;
- (i) after the step (h), forming the first and second memory gate electrodes over both the sidewalls of the first and second control gate electrodes by patterning the conductive film formed over the second gate insulation film;
- (j) after the step (i), removing the sidewall;
- (k) after the step (j);
- removing one of the first and second memory gate electrodes formed over both the sidewalls of each of the first and second control gate electrodes;
- (l) after the step (k), leaving the second gate insulation film between the sidewalls of the first and second control gate electrodes and the first and second memory gate electrodes and between the well and the first and second memory gate electrodes by patterning the second gate insulation film;
- and
- (m) after the step (l), forming source and drain regions of a second conductivity type functioning as the conductivity type opposite to the first conductivity type of the first and second memory cells respectively in the well,
- wherein the first memory gate electrode is formed so as to have a gate length longer than the gate length of the second memory gate electrode.
A method for producing a semiconductor device including a first memory cell having a first control gate electrode and a first memory gate electrode and a second memory cell having a second control gate electrode and a second memory gate electrode, the first and second memory cells being formed over the main face of a semiconductor substrate,
- the method comprising the steps of:
- (a) forming a well of a first conductivity type over the semiconductor substrate;
- (b) forming a first gate insulation film over the well;
- (c) forming the first and second control gate electrodes through the first gate insulation film;
- (d) after the step (c), forming a second gate insulation film over the main face of the semiconductor substrate;
- (e) after the step (d), forming a conductive film over the main face of the semiconductor substrate;
- (f) after the step (e), covering the region ranging from a part of the top face of the first control gate electrode to the region ranging from a sidewall on one side of the first control gate electrode to the semiconductor substrate in the vicinity of the first control gate electrode with a photoresist;
- (g) after the step (f), by patterning the conductive film formed over the second gate insulation film, forming the first memory gate electrode comprised of the conductive film over a side face of one side of the first control gate electrode, forming a side wall comprised of the conductive film over the sidewall on the other side of the first control gate electrode at the lower part of the photoresist, forming a second memory gate electrode over both the sidewalls of the second control gate electrode, and thereafter removing the photoresist;
- (h) after the step (g), removing the sidewall and the second memory gate electrode over the sidewall on one side of the second control gate electrode;
- (i) after the step (h), leaving the second gate insulation film between the sidewalls of the first and second control gate electrodes and the first and second memory gate electrodes and between the semiconductor substrate and the first and second memory gate electrodes by patterning the second gate insulation film;
- and
- (j) after the step (i), forming source and drain regions of a second conductivity type functioning as the conductivity type opposite to the first conductivity type of the first and second memory cells in the well, respectively,
- wherein the first memory gate electrode is formed so as to have a gate length longer than the gate length of the second memory gate electrode.
Dependencies are inferred from the claim text.