US 2010/0301402 A1 · SEMICONDUCTOR DEVICE · patentgrep

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Abstract

Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar.

Claims41

Dependent claims

A semiconductor device comprising:

a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar provided underneath the first silicon pillar;
and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region;
and
the third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein:
the first-conductive type impurity region of the second silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the second silicon pillar;
and
the first-conductive type impurity region of the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the third silicon pillar.

11 more elements

A semiconductor device comprising:

a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar provided underneath the first silicon pillar;
and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region;
and
the third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein:
each of the first-conductive type impurity region of the second silicon pillar and the first-conductive type impurity region of the third silicon pillar has a length which is short enough to allow the second-conductive type high-concentration impurity region of the second silicon pillar and the second-conductive type high-concentration impurity region of the third silicon pillar to be formed.

9 more elements

A semiconductor device comprising:

a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar provided underneath the first silicon pillar;
and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the second silicon pillar is formed as a second-conductive type high-concentration impurity region;
and
the third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein the first-conductive type impurity region of the third silicon pillar has a length which is short enough to allow the second-conductive type high-concentration impurity region of the second silicon pillar and the second-conductive type high-concentration impurity region of the third silicon pillar to be formed.

8 more elements

A semiconductor device comprising:

a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar provided underneath the first silicon pillar;
and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the third silicon pillar is formed as a second-conductive type high-concentration impurity region formed therein;
and
the second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the second silicon pillar,
and wherein the first-conductive type impurity region of the second silicon pillar has a length which is short enough to allow the second-conductive type high-concentration impurity region of the third silicon pillar and the second-conductive type high-concentration impurity region of the second silicon pillar to be formed.

8 more elements

A semiconductor device comprising:

a first-conductive type first silicon pillar formed on a first-conductive type silicon substrate:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the silicon substrate has a second-conductive type high-concentration impurity region formed in a part thereof;
and
the third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein the first-conductive type impurity region of the third silicon pillar has a length which is short enough to allow the second-conductive type high-concentration impurity region of the third silicon pillar to be formed.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/787,929Filed 26 May 2010
Priority: JP 2009-13058329 May 2009
Published: 2 Dec 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/519
Characterised by the conducting layers: characterised by their top-view geometrical layouts
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 30/031
Of FETs having insulated gates [IGFET]: of thin-film transistors [TFT]
H10D 30/0318
Of thin-film transistors [TFT]: of vertical TFTs

Family

Application61/217,595Us provisional application · filed 2 Jun 2009
US 8,502,303 B2Related patent
US 2010/0301402 A1This patent

From the US filing history. Foreign family members aren’t listed.

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