Tri-Gate Field-Effect Transistors Formed By Aspect Ratio Trapping

A structure comprising:

• a dielectric layer disposed over a semiconductor substrate comprising a first semiconductor material;
• a trench disposed in the dielectric layer and (i) extending to a surface of the substrate, (ii) being defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, and (iii) having a width w;
• a crystalline material at least partially disposed in the trench, the crystalline material including a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material, a side portion of the crystalline material extending above the dielectric layer;
• and
• a gate disposed over the crystalline material,
• wherein (i) a ratio of the height h to the width w is ≧0.5, (ii) a majority of dislocation defects in the crystalline material terminate at or below the predetermined distance H, (iii) h≧H, and (iv) the third semiconductor material includes a strained channel.

A semiconductor device comprising:

• a defect trapping region comprising a trench, the trench including a dielectric sidewall, the defect trapping region being defined proximate a substrate, the substrate having a first lattice constant;
• a semiconductor material disposed within the defect trapping region, the semiconductor material having a second lattice constant different from the first lattice constant, a majority of crystalline defects in the semiconductor material terminating within the defect trapping region;
• a fin having a semiconducting sidewall and a top surface, the fin being disposed above the semiconductor material disposed within the defect trapping region;
• and
• a transistor gate disposed over the semiconducting sidewall and the top surface.

A semiconductor structure comprising:

• a dielectric layer over a semiconductor substrate, the dielectric layer having an opening extending below a top surface of the dielectric layer, the opening being defined by a dielectric sidewall;
• a crystalline material disposed at least partially in the opening, the crystalline material comprising a first material different from and contacting the semiconductor substrate, the crystalline material extending above the top surface of the dielectric layer to define a crystalline sidewall, a majority of crystalline defects in the crystalline material terminating below the top surface of the dielectric layer;
• and
• a gate dielectric over the crystalline material and on the crystalline sidewall.