US 2010/0301304 A1 · BURIED SILICIDE STRUCTURE AND METHOD FOR MAKING

Abstract

Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Claims21

Dependent claims

A method for manufacturing an integrated circuit device, the method comprising:

forming a semiconductor body comprising silicon;
forming a plurality of trenches in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls;
depositing a silicide precursor within the trenches to contact the sidewalls of the semiconductor lines;
removing a portion of the silicide precursor to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls;
and
forming silicide conductors by inducing reaction of the strips of silicide precursor with the silicon of the semiconductor lines.

3 more elements

A memory device comprising:

a first array of memory cells underlying a second array of memory cells, the first and second array of memory cells separated from one another by an insulator layer, the first and second arrays of memory cells each comprising:
a plurality of word lines comprising doped silicon material, and silicide conductors below top surfaces of the doped silicon material;
a plurality of bit lines overlying the word lines;
and
a plurality of memory cells located between the bit lines and word lines, memory cells in the plurality of memory cells comprising:
a diode;
and
a programmable resistance memory element programmable to a plurality of resistance states;
and
bias circuitry to apply bias arrangements across the diode and the memory element of a selected memory cell in the plurality of memory cells of a particular array of memory cells, the bias arrangements including:
a first bias arrangement to change the resistance state of the memory element of the selected memory cell from a first resistance state to a second resistance state;
and
a second bias arrangement to change the resistance state of the memory element of the selected memory cell from the second resistance state to the first resistance state.

10 more elements

Dependencies are inferred from the claim text.

Buried silicide structure and method for making

Life of this patent

Buried silicide structure and method for making

Life of this patent

Abstract

Claims21