Lock-free scheduler with priority support
AssigneeMicrosoft Corporation
InventorsArun U. Kishan, Thomas D. I. Fahrig, Rene Antonio Vega
Life of this patent
Estimating the term…
Abstract
Techniques for implementing a lock-free scheduler with ordering support are described herein. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects of the present disclosure; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer.
Claims20
A computer readable storage medium including processor executable instructions, the computer readable storage medium comprising:
- instructions for storing a thread in a linked list associated with a specific processor of a plurality of processors in a computer system, the linked list accessible to the plurality of processors;
- instructions for adding the thread stored in the linked list to a ready list associated with the specific processor, the ready list is only accessible to the specific processor and the threads are stored in the ready list in an order of priority;
- and
- instructions for executing the thread.
A computer system, comprising:
- circuitry for determining that a linked list for a processor is empty, the linked list configured to store threads;
- circuitry for adding a thread to the linked list and sending an interrupt to the processor;
- circuitry for determining that the thread was added to the linked list for the processor in response to receiving the interrupt;
- and
- circuitry for adding the thread to a ready list for the processor, the processor configured to execute threads from the ready list in an order of thread priority, and the ready list is exclusively accessible by the processor.
A method, comprising:
- entering, by a processor, an idle state, wherein the processor is configured to monitor a memory address associated with a linked list while in the idle state;
- detecting, by the processor, that a thread was added to the linked list and exiting the idle state;
- and
- adding the thread to a ready list for the processor, the processor configured to execute threads from the ready list in an order of priority and the ready list is exclusively accessible by the processor.
Dependencies are inferred from the claim text.