Method, system and application for sequential cofactor-based analysis of netlists
AssigneeInternational Business Machines Corporation
InventorsJASON R. BAUMGARTNER, ROBERT L. KANZELMAN, HARI MONY, VIRESH PARUTHI
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Abstract
Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.
Claims18
A method of sequential cofactor-based circuit design for a sequential circuitry netlist, the method comprising:
- selecting an arbitrary gate of the sequential circuitry for analysis;
- configuring the sequential circuitry netlist to connect the arbitrary gate to a multiplexer;
- configuring the sequential circuitry netlist to connect selector control circuitry to a selector input of the arbitrary gate;
- detecting a ctime signal applied to said selector input;
- in response to the ctime signal, setting the multiplexer output to alter the arbitrary gate output;
- and
- determining whether the sequential circuitry behavior remains equivalent during time that the multiplexer output is set to alter the arbitrary gate output.
A software product comprising a program of instructions stored on a machine readable device for sequential cofactor-based circuit design of a sequential circuitry netlist wherein the program of instructions upon being executed on a computer causes the computer to perform activities comprising:
- selecting an arbitrary gate of the sequential circuitry for analysis;
- configuring the sequential circuitry netlist to connect the arbitrary gate to a multiplexer;
- configuring the sequential circuitry netlist to connect selector control circuitry to a selector input of the arbitrary gate;
- detecting a ctime signal applied to said selector input;
- in response to the ctime signal, setting the multiplexer output to alter the arbitrary gate output;
- and
- determining whether the sequential circuitry behavior remains equivalent during time that the multiplexer output is set to alter the arbitrary gate output.
Dependencies are inferred from the claim text.