Circuit description generating apparatus and function verification method
AssigneeKabushiki Kaisha Toshiba
InventorTakeo Nishide
Life of this patent
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Abstract
A circuit description generating apparatus has an ID addition part configured to add a common ID to a command inputted to a verification target circuit described by a circuit description language and data corresponding to the command, a bit width adjusting part configured to adjust a bit width of an ID of the command and an ID of the data along a signal path which pass through inside of the verification target circuit, and a circuit description generating part configured to generate a circuit description corresponding to the verification target circuit, the circuit description including the command and data with the IDs of which bit widths are adjusted by the bit width adjusting part.
Claims20
A circuit description generating apparatus, comprising:
- an ID addition module configured to add a common ID to a command to a verification target circuit described by a circuit description language and data corresponding to the command;
- a bit width adjusting module configured to adjust a bit width of an ID of the command and an ID of the data along a signal path configured to pass through inside of the verification target circuit;
- and
- a circuit description generator configured to generate a circuit description corresponding to the verification target circuit, the circuit description comprising the command and data with the IDs comprising bit widths adjusted by the bit width adjusting module.
A function verification method, comprising:
- adding a common ID to a command to a verification target circuit described by a circuit description language and data corresponding to the command;
- adjusting a bit width of an ID of the command and an ID of the data along a signal path passing through inside of the verification target circuit;
- and
- generating a circuit description corresponding to the verification target circuit, the circuit description comprising the command and data with the IDs comprising adjusted bit widths.
Dependencies are inferred from the claim text.