Semiconductor substrate wiring design support device and control method thereof

A method of controlling a semiconductor substrate wiring design support device that includes a memory unit storing logical connection information, the method comprising:

• using a computer processor designing wiring for a semiconductor substrate based on the logical connection information;
• providing a single via between a first wire layer and a second wire layer when the wiring is a wire between the first wire layer and the second wire layer;
• detecting the single via as an isolated-via-error when only the single via is provided in a case where a plurality of vias are needed according to a via alteration rule;
• altering the single via detected as the isolated-via-error to an isolated-via-error-treatment via with a plurality of vias;
• and
• altering a single via of vias held by the wire wired on the semiconductor substrate, to a redundancy via with a plurality of vias after the alteration to the isolated-via-error-treatment via.

A computer readable recording medium that stores a program for controlling a semiconductor substrate wiring design support device that includes a memory unit storing logical connection information and an arithmetic processing unit, the computer readable recording medium causing the arithmetic processing unit to execute operations comprising:

• designing wiring for a semiconductor substrate based on the logical connection information;
• providing a single via between a first wire layer and a second wire layer when the wiring is a wire between the first wire layer and the second wire layer;
• detecting the single via as an isolated-via-error when only the single via is provided in a case where a plurality of vias are needed according to a via alteration rule;
• altering a single via, detected as the isolated-via-error, to an isolated-via-error-treatment via with a plurality of vias;
• and
• altering a single via of vias held by the wire wired on the semiconductor substrate, to a redundancy via with a plurality of vias after the alteration to the isolated-via-error-treatment via.