Memory controller and semiconductor memory apparatus
AssigneeKabushiki Kaisha Toshiba
InventorsMichiko TAKAHASHI, Kenji Sakaue, Hiroshi Sukegawa
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AssigneeKabushiki Kaisha Toshiba
InventorsMichiko TAKAHASHI, Kenji Sakaue, Hiroshi Sukegawa
Estimating the term…
A memory controller that has an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number; an error threshold level storage section that stores an error threshold level for each block; an uncorrected number measurement section that measures an uncorrected number of an error correction for each block; an error threshold level modification section that, each time an uncorrected number of a certain block exceeds a predetermined number, modifies the error threshold level of the block; an encoder that performs encoding processing of data stored in memory cells belonging to each block with an error correction number that is based on an error threshold level and the error correction number correspondence table; and a decoder that performs decoding processing of data.
A memory controller configured to control an error correction for a flash memory section, comprising:
A semiconductor memory apparatus, comprising:
A semiconductor memory apparatus, comprising:
Dependencies are inferred from the claim text.