Method and apparatus for efficient memory allocation for turbo decoder input with long turbo codeword
AssigneeQUALCOMM Incorporated
InventorsThomas Sun, Jing Jiang, Xinmiao Zhang, Fuyun Ling
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Abstract
A method and apparatus for memory allocation for turbo decoder input with a long turbo codeword, the method comprising computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR; storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory; and reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.
Claims40
A method for memory allocation for turbo decoder input with a long turbo codeword, the method comprising:
- computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR;
- storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory;
- and
- reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.
An apparatus for memory allocation for turbo decoder input with a long turbo codeword, the apparatus comprising a processor and a memory, the memory containing program code executable by the processor for performing the following:
- computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR;
- storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory;
- and
- reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.
An apparatus for memory allocation for turbo decoder input with a long turbo codeword, the apparatus comprising:
- means for computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR;
- means for storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory;
- and
- means for reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.
A computer-readable medium storing a computer program, wherein execution of the computer program is for:
- computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR;
- storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory;
- and
- reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.
Dependencies are inferred from the claim text.