Failure prediction circuit and method, and semiconductor integrated circuit

A failure prediction circuit comprising:

• a delay circuit having an input connected to a data line, the delay circuit delaying an input signal by a predetermined delay time to output the delayed signal;
• first and second storage circuits having data input terminals respectively connected to the input and the output of the delay circuit;
• and
• a determination circuit that compares outputs of the first and second storage circuits to determine whether or not the outputs of the first and second storage circuits coincide;
• wherein
• the first and second storage circuits have respective clock input terminals connected in common to a clock line, and store logic levels of the respective data input terminals at a time point when the clock line transitions from a first logic level to a second logic level, and output the stored logic levels.

A failure prediction circuit comprising:

• a delay circuit having an input connected to a clock line, the delay circuit delaying an input signal by a predetermined delay time to output the delayed signal;
• first and second storage circuits having data input terminals connected in common to a data line and having clock input terminals respectively connected to the input to and the output of the delay circuit;
• and
• a determination circuit comparing outputs of the first and second storage circuits to determine whether or not the outputs of the first and second storage circuits coincide;
• wherein
• the first and second storage circuits store logic levels of the data input terminals at time points when the respective clock input terminals thereof transition from a first logic level to a second logic level to output the stored logic levels.

A failure prediction circuit comprising:

• first and second storage circuits having data input terminals connected in common to a data line and having clock input terminals connected in common to a clock line, the first and second storage circuits respectively storing logic levels of the data input terminals at a time point when the clock input terminals thereof transition from a first logic level to a second logic level to output respectively the stored logic levels;
• and
• a determination circuit comparing the outputs of the first and second storage circuits to determine whether or not the outputs of the first and second storage circuits coincide;
• wherein
• a logic threshold by which the first storage circuit determines a logic level of the data line and a logic threshold by which the second storage circuit that determines a logic level of the data line are set to values that are different to each other.

A pipeline register circuit comprising:

• first and second storage circuit, each storage circuit sampling an input data signal in response to an input clock signal to output the sampled data signal;
• and
• a determination circuit determining whether or not the outputs of the first and second storage circuits coincide;
• at least one of input timings of the data signal, input timings of the clock signal, and input logic thresholds of the data signal being set to be different from each other between the first and second storage circuits in data sampling,
• the output of a predetermined one of the first and second storage circuits being set to register output data.

A failure prediction method, wherein first and second storage circuits are provided as registers, each of the registers receiving a data signal output from an operation circuit, sampling the data signal in response to an input clock signal to output the sampled data signal;

• the method comprising:
• setting at least one of input timings of the data signal, input timings of the clock signal, and input logic thresholds of the data signal to be different from each other between the first and second storage circuits in data sampling;
• comparing the output of the first storage circuit with the output of the second storage circuit when a logic level of a clock line transitions from a first logic level to a second logic level;
• and
• predicting a type of a failure or a failure location in the operation circuit, based on a comparison result of the outputs of the first storage circuit and the second storage circuit.