High Speed Clock Control
AssigneeMentor Graphics Corporation
InventorsFriedrich HAPKE, Michael Wittke, Sascha Ochsenknecht, Thomas H. Rinderknecht
Life of this patent
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Abstract
On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period.
Claims9
An integrated circuit for clock control, comprising:
- a glitch-elimination module that generates a first glitch-free clock waveform for clock systems of a core logic circuit in a shift operation of a logic test of the core logic circuit;
- and
- a plurality of clock control modules that generate a plurality of glitch-free clock waveforms for the clock systems of the core logic circuit in a capture operation of the logic test of the core logic circuit, each of the plurality of clock control modules including:
- a clock control sub-module that generates clock enabling pulses based on a clock control signal and a clock signal;
- a glitch-elimination sub-module that generates, based on the clock enabling pulses, a second glitch-free clock waveform with 0 to k pulses for one of the clock systems of the core logic circuit in the capture operation;
- and
- a combination sub-module that combines the first glitch-free clock waveform and the second glitch-free clock waveform with 0 to k pulses.
An integrated circuit, comprising:
- a core logic circuit;
- a high speed clock control circuit that based on a clock control signal, activates certain high speed clocks with predefined waveforms during a capture period of a logic test, clock output ports of the high speed clock control circuit being connected to clock input ports of the core logic circuit;
- and
- a clock generation unit that generates a plurality of clock signals being supplied to clock input ports of the high speed clock control circuit.
Dependencies are inferred from the claim text.