US 2010/0251016 A1 · Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies

Abstract

A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.

Claims20

Dependent claims

A method, in a processing device, for issuing instructions, the method comprising:

receiving an instruction for dispatch to one of a plurality of execution units in the processing device;
analyzing a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register;
responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, storing a tag corresponding to the instruction in the tag register;
and
dispatching the instruction to an issue queue for issue to the one of the plurality of execution units.

2 more elements

A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive an instruction for dispatch to one of a plurality of execution units;
analyze a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register;
responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, store a tag corresponding to the instruction in the tag register;
and
dispatch the instruction to an issue queue for issue to the one of the plurality of execution units.

2 more elements

An information handling system, comprising:

at least one processor;
and
a memory coupled to the at least one processor, wherein the memory comprises instructions which, when executed by the at least one processor, cause the at least one processor to:
receive an instruction for dispatch to one of a plurality of execution units;
analyze a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register;
responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, store a tag corresponding to the instruction in the tag register;
and
dispatch the instruction to an issue queue for issue to the one of the plurality of execution units.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/409,981Filed 24 Mar 2009

Published

30 Sep 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 11/0793
Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of…
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/3863
Recovery, e.g. branch miss-prediction, exception handling: using multiple copies of the architectural state, e.g. shadow registers

Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies

Life of this patent

Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies

Life of this patent

Abstract

Claims20