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US 2010/0251014 A1Published application
Computer and failure handling method thereof
AssigneeHitachi, Ltd.
InventorNobuo YAGI
Life of this patent
Estimating the term…
Abstract
A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred.
Claims12
A computer comprising:
- a memory that stores a BIOS;
- a CPU that executes the BIOS;
- and
- a root port connected to the CPU through a primary bus and to a PCI express path through a secondary bus, the root port functioning as a PCI express bridge;
- wherein the root port detects a failure on the PCI express path, and then issues a SMI (System Maintenance Interrupt) to the CPU;
- and
- on the receipt of the SMI, the CPU executes the BIOS to issue, through the root port, a PCI express reset to the PCI express path on which the failure has occurred.
4 more elements
A computer system comprising:
- a plurality of blade computers, each of which includes a memory that stores a BIOS;
- a CPU that executes the BIOS;
- and a root port connected to the CPU through a primary bus and to a PCI express path through a secondary bus, the root port functioning as a PCI express bridge;
- and
- a PCI express switch and a PCI express device which constitute the PCI express path;
- wherein each of the blade computers is configured such that the root port detects a failure on the PCI express path, and then issues a SMI (System Maintenance Interrupt) to the CPU;
- and
- on the receipt of the SMI, the CPU executes the BIOS to issue, through the root port, a PCI express reset to the PCI express path on which the failure has occurred.
5 more elements
A method of handling a failure in a computer,
- the computer comprising:
- a memory that stores a BIOS and a device driver for controlling a PCI express device;
- a CPU that executes the BIOS and the device driver;
- and
- a root port connected to the CPU through a primary bus and to a PCI express path through a secondary bus, the root port functioning as a PCI express bridge;
- wherein the root port detects a failure on the PCI express path, and then issues a SMI (System Maintenance Interrupt) to the CPU;
- the CPU, on the receipt of the SMI, executes the BIOS to issue, through the root port, a PCI express reset to the PCI express path on which the failure has occurred;
- and
- the CPU executes the device driver to detect a PCI express device included in the PCI express path that has received the PCI express reset, and then to disable the use of the detected PCI express device.
6 more elements
Dependencies are inferred from the claim text.