Multiprocessor system and failure recovering system

A node controller assigned with a unique identifier and provided for a node, comprising:

• a first request control section configured to determine the identifier of a transmission destination of a request based on a memory address of an access destination of said request;
• a second request control section configured to determine the identifier of the transmission destination of said request based on the memory address of the access destination of said request;
• a first register configured to hold in said first request control section, the identifier of the transmission destination of said request to be outputted,
• a second register configured to hold in said second request control section, the identifier of the transmission destination of said request to which said request should be outputted;
• a first routing table configured to specify one of said first request control section and said second request control section as an output destination of said request based on the identifier held by said first register, the identifier held by said second register, the identifier of the transmission destination of said request, when receiving said request;
• and
• a second routing table configured to specify a signal line for the identifier of the transmission destination of said request based on the identifier of the transmission destination which is determined by said first request control section or said second request control section, to transmit said request, and
• wherein each of said plurality of nodes comprises said plurality of processors, a plurality of memories respectively connected to said plurality of processors, and first and second node controllers provided for a redundant configuration and connected with said plurality of processors, and identifiers are assigned to said plurality of processors, said first node controller and said second node controller in each node.

A failure recovering method in a multiprocessor system which comprises a plurality of nodes, wherein each of said plurality of nodes comprises a plurality of processors, a plurality of memories respectively connected to said plurality of processors, and first and second node controllers provided for a redundant configuration and connected with said plurality of processors, and wherein unique identifiers are assigned to said plurality of processors, said first node controller and said second node controller in each node,

• wherein said failure recovering method comprises:
• determining by a first request control section, the identifier of a transmission destination of a request based on a memory address of an access destination of said request;
• determining by a second request control section, the identifier of the transmission destination of said request based on the memory address of the access destination of said request;
• holding by a first register, in said first request control section, the identifier of the transmission destination of said request to which said request should be outputted;
• holding by a second register, in said second request control section, the identifier of the transmission destination of said request to which said request should be outputted;
• specifying by a first routing table, one of said first request control section and said second request control section as an output destination of said request based on the identifier held by said first register, the identifier held by said second register, the identifier of the transmission destination of said request, when receiving said request;
• and
• specifying by a second routing table, a signal line for the identifier of the transmission destination of said request based on the identifier of the transmission destination which is determined by said first request control section or said second request control section, to transmit said request.