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US 2010/0251001 A1Published application
Enabling Resynchronization Of A Logic Analyzer
AssigneeIntel Corporation
InventorsKeith Drescher, Debendra Das Sharma, David Sams, Richard Glass
Life of this patent
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Abstract
In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a first semiconductor device including a physical layer to enable communication along a link coupled between the first semiconductor device and a second device, the physical layer including a state machine to enable retraining of the link, wherein the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link, the external input to indicate that the logic analyzer has lost synchronization with respect to link communications and the retraining is to enable the logic analyzer to regain the synchronization.
An apparatus comprising:
- a transmitter coupled to a link on which communications proceed according to a scrambling protocol which lacks a periodic uniquely recognizable sequence, the link coupled between the transmitter and a receiver, the transmitter including a physical layer to periodically send an unscrambled ordered set along the link to enable a logic analyzer coupled to the link to regain synchronization with respect to the communications, wherein the unscrambled ordered set includes a synchronization header, a first predetermined bit sequence, a second predetermined bit sequence and a value from a scrambling register of the transmitter.
A method comprising:
- receiving an unscrambled ordered set in a logic analyzer coupled to a link, the unscrambled ordered set generated and transmitted by a transmitting agent at a periodic interval, wherein communications proceed along the link according to a scrambling protocol which lacks a periodic uniquely recognizable sequence;
- processing the unscrambled ordered set to confirm a valid unscrambled ordered set;
- setting one or more de-scrambling registers of the logic analyzer responsive to a scrambling register value passed in the unscrambled ordered set to resynchronize the logic analyzer to the communications;
- and
- verifying resynchronization of the logic analyzer.
2 more elements
Dependencies are inferred from the claim text.