System and Method of Routing Instructions

A superscalar processor, comprising:

• a first instruction issue queue including a plurality of entries;
• a steering unit coupled to the first instruction issue queue;
• a second instruction issue queue coupled to the steering unit and including a plurality of entries;
• and
• a plurality of execution pipelines coupled to the second instruction issue queue and including at least a branch execution pipeline and at least two non-branch execution pipelines;
• wherein the steering unit provides logic for performing the functions of:
• receiving a plurality of ordered instructions that pass into instruction issue queue entries of the first instruction issue queue;
• determining that at least a first instruction and a second instruction of the plurality of ordered instructions are non-branching instructions, wherein the second instruction is subsequent to the first instruction;
• storing the first instruction and the second instruction in two non-branching instruction issue queue entries of the second instruction issue queue;
• determining whether or not a third instruction of the plurality of ordered instructions is a branch instruction, wherein the third instruction is subsequent to the second instruction;
• if the third instruction is a branch instruction, storing the third instruction in a branch entry of the second instruction issue queue;
• and
• if the third instruction is not a branch instruction, storing a no operation (NOP) instruction in the branch entry of the second instruction issue queue.

A processor system, comprising:

• a memory;
• and
• at least one superscalar processor coupled to the memory, wherein the at least one superscalar processor includes:
• a first instruction issue queue including a plurality of entries;
• a steering unit coupled to the first instruction issue queue;
• a second instruction issue queue coupled to the steering unit and including a plurality of entries;
• and
• a plurality of execution pipelines coupled to the second instruction issue queue and including at least a branch execution pipeline and at least two non-branch execution pipelines;
• wherein the at least one superscalar processor provides logic for performing the functions of:
• receiving a plurality of ordered instructions from the memory;
• and
• storing the plurality of ordered instructions in issue queue entries of the first instruction issue queue;
• and
• wherein the steering unit provides logic for performing the functions of:
• receiving the plurality of ordered instructions that pass into instruction issue queue entries of the first instruction issue queue;
• determining that at least a first instruction and a second instruction of the plurality of ordered instructions are non-branching instructions, wherein the second instruction is subsequent to the first instruction;
• storing the first instruction and the second instruction in two non-branching instruction issue queue entries of the second instruction issue queue;
• determining whether or not a third instruction of the plurality of ordered instructions is a branch instruction, wherein the third instruction is subsequent to the second instruction;
• if the third instruction is a branch instruction, storing the third instruction in a branch entry of the second instruction issue queue;
• and
• if the third instruction is not a branch instruction, storing a no operation (NOP) instruction in the branch entry of the second instruction issue queue.