US 2010/0250900 A1Published application

Dependency tracking for enabling successive processor instructions to issue

AssigneeInternational Business Machines Corporation

InventorsMary Douglass Brown, William Elton Burky, Dung Quoc Nguyen, Balaram Sinharoy

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Abstract

An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

Claims25

Dependent claims

A method of processing instructions, comprising:

decoding, by a decoder, instructions in a stream of instructions, some instructions of which exhibit dependencies, the instructions including a producer instruction and a consumer instruction;
dispatching, by a dispatch unit, a producer instruction to a non-shifting issue queue (NSIQ) in an issue unit;
dispatching, by the dispatch unit, a consumer instruction to a shifting issue queue (SIQ) in the issue unit;
storing, by the NSIQ, producer instruction queue position information for the producer instruction;
storing, by the SIQ, consumer instruction queue position information for the consumer instruction;
issuing, by the issue unit, the producer instruction;
testing, by the issue unit, to determine if the producer instruction queue position information matches the consumer instruction queue position information;
and
issuing, by the issue unit, the consumer instruction consecutively with respect to the producer instruction if the producer instruction queue position information matches the consumer instruction queue position information.

6 more elements

A processor, comprising:

a decoder that decodes instructions in a stream of instructions, some instructions of which exhibit dependencies, the instructions including a producer instruction and a consumer instruction;
a dispatch unit, coupled to the decode unit, that dispatches a producer instruction to a non-shifting issue queue (NSIQ) in an issue unit, the dispatcher dispatching a consumer instruction to a shifting issue queue (SIQ) in the issue unit, the issue unit being coupled to the dispatch unit;
wherein the NSIQ stores producer instruction queue position information for the producer instruction;
wherein the SIQ stores consumer instruction queue position information for the consumer instruction;
a first test circuit, situated in the issue unit, that tests to determine if the producer instruction queue position information matches the consumer instruction queue position information, and in response to the test the issue unit issues the consumer instruction consecutively with respect to the producer instruction if the producer instruction queue position information matches the consumer instruction queue position information.

2 more elements

An information handling system (IHS), comprising:

a memory that provides a stream of instructions, some instructions of which exhibit dependencies, the instructions including a producer instruction and a consumer instruction;
a processor, coupled to the memory, the processor including:
a decoder that decodes instructions in a stream of instructions, some instructions of which exhibit dependencies, the instructions including a producer instruction and a consumer instruction;
a dispatch unit, coupled to the decode unit, that dispatches a producer instruction to a non-shifting issue queue (NSIQ) in an issue unit, the dispatcher dispatching a consumer instruction to a shifting issue queue (SIQ) in the issue unit, the issue unit being coupled to the dispatch unit;
wherein the NSIQ stores producer instruction queue position information for the producer instruction;
wherein the SIQ stores consumer instruction queue position information for the consumer instruction;
a first test circuit, situated in the issue unit, that tests to determine if the producer instruction queue position information matches the consumer instruction queue position information, and in response to the test the issue unit issues the consumer instruction consecutively with respect to the producer instruction if the producer instruction queue position information matches the consumer instruction queue position information.

4 more elements

Dependencies are inferred from the claim text.