Addressing Device for Parallel Processor
AssigneeThales
InventorGérard Gaillat
Life of this patent
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Abstract
The invention relates to a parallel processor which comprises elementary processors (3) disposed according to a topology with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction relating to at least one operand and/or providing at least one result. The instruction comprises, for each operand and/or each result, information relating to the position of a field of action within a data structure of the table of dimension M type and the parallel processor comprises means (41, 42, 43) for calculating the address of each operand and/or each result within each elementary processor, as a function of the position of the field of action and of the position of the elementary processor within the topology.
Claims22
A parallel processor which comprises elementary processors (3) each comprising at least one calculating unit and at least one memory which comprises memory-words, and disposed according to a topology, with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction comprising the reading of at least one operand and/or comprising the writing of at least one result, characterized in that the instruction defines the set of reads and/or the set of writes of the elementary processors, each in its own memory, as being a read and/or a write in a field of action, a field of action being a set of memory-words at the rate of one memory-word per elementary processor, this memory-word being located in the memory of the elementary processor, a field of action of an operand being the set of memory-words read by the elementary processors, each in its own memory, in order to acquire this operand, a field of action of a result being the set of memory-words written by the elementary processors, each in its own memory, in order to store this result, in that the instruction comprises, for each operand and/or each result, information relating to the position of this field of action, in that the position of the field of action is defined as being a position within a unique data structure of the table of dimension N type, N being an integer equal to or greater than 1, and in that this table is distributed over the memories of the different elementary processors.
The parallel processor as claimed in the preceding claim, characterized in that it comprises means of calculating the address of each operand and/or each result within each elementary processor, as a function of the position of the field of action and of the position of the elementary processor within the topology.
The parallel processor as claimed in the preceding claim, characterized in that it comprises means (50) of calculating the position of the field of action as a function of said information, connected to the means of calculating the address.
The parallel processor as claimed in one of the preceding claims, characterized in that the elementary processors are disposed according to a topology having P dimensions, P being an integer greater than or equal to 1.
The parallel processor as claimed in one of the preceding claims, characterized in that, with the elementary processors being disposed according to a topology having at least one dimension, for each dimension the means of calculation of the address of the element of the data structure which relates to an elementary processor, whose x coordinate is p according to said dimension, are obtained by combination of a value related to the position of the field and a value related to the position of the elementary processor.
The parallel processor as claimed in one of the preceding claims, characterized in that, with the field of action having ends defined by their coordinates, the position of the field of action is defined by the position of a barycenter obtained by linear combination of these ends, the sum of the significances of the ends being equal to 1.
The parallel processor as claimed in one of the preceding claims, characterized in that, with the field of action having ends defined by their coordinates, the position of the field of action is defined by the position of the end whose coordinates are minimal.
The parallel processor as claimed in the preceding claim, characterized in that, with the processors being disposed according to a topology having at least one dimension, for each dimension the means of calculating the address of the element of the data structure which relates to a PE, whose x coordinate is p according to said dimension, comprise means of calculating:
- Ad=Int((Wmin+Np−1−p)/Np),
- Np being the number of elementary processors in question on said dimension, Wmin being defined on said dimension as a function of the coordinates of said position.
The parallel processor as claimed in the preceding claim, characterized in that the processors are disposed according to a topology having one dimension and the data structure is mono-dimensional and in that the position of the field of action is defined by Xmin and Wmin=Xmin.
The parallel processor as claimed in the preceding claim, characterized in that. Np being a power of 2, the means of calculating Ad comprise means in order to:
- Add Xmin and (Np−1−p),
- Delete the last LNp bits of the result. LNp being the base 2 logarithm of Np.
The parallel processor as claimed in the preceding claim, characterized in that. Np and Lx being powers of 2, the means of calculating Ad comprise means in order to:
- Add Xmin and (Np−1−p),
- Delete the last LNp bits of the result. LNp being the base 2 logarithm of Np,
- Concatenate in the least significant positions the preceding quantity represented over LLx−LNp bits and Ymin in the most significant positions, LLx being the base 2 logarithm of Lx.
The parallel processor as claimed in the preceding claim,
- characterized in that, Np, Lx and Ly being powers of 2, the means of calculating Ad comprise means in order to:
- Add Xmin and (Np−1−p),
- Delete the last LNp bits of the result. LNp being the base 2 logarithm of Np,
- Concatenate in the least significant positions the preceding quantity represented over LLx−LNp bits, in medium significant positions Ymin represented over Ly bits and in the most significant positions Zmin represented over Lz bits, LLx being the base 2 logarithm of Lx.
The parallel processor as claimed in the preceding claim,
- characterized in that, Nx, Ny, Lx and Ly being powers of 2, LLx and LLy being the base 2 logarithms of Lx and Ly respectively, the means of calculating Ad comprise means to:
- Add Xmin and (Nx−1−px).
- Delete the last LNx bits of the result. LNx being the base 2 logarithm of Nx, Adx is obtained on LLx−LNx bits,
- Add Ymin and (Ny−1−py),
- Delete the last LNy bits of the result. LNy being the base 2 logarithm of Ny. Ady is obtained on LLy−LNy bits,
- Concatenate in the least significant positions Adx represented on LLx−LNx bits, and in the most significant positions Ady represented on LLy−LNy bits.
The parallel processor as claimed in one of the preceding claims, characterized in that the parallel processor is a computer of the SIMD type.
Dependencies are inferred from the claim text.