Version based non-volatile memory translation layer
AssigneeMicron Technology, Inc.
InventorWanmo Wong
Life of this patent
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Abstract
A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows.
Claims20
A memory device comprising:
- a memory array having a plurality of memory cells arranged in a plurality of data groups, wherein each data group is identified by a data group identification and contains a version data field comprising a version number that indicates a version of a particular data group identification;
- and
- a control circuit, wherein the control circuit is configured to access a data group by translating a logical address of the data group to a physical sector address of the memory array using a version number stored in the version number data field of the data group.
A system comprising:
- a host coupled to a non-volatile memory device, wherein the host is configured to store logical sectors of data in the memory device such that each logical sector is identified by a logical sector ID and each logical sector ID is stored in an address translation table in memory with an associated version number to identify a particular physical address.
Dependencies are inferred from the claim text.