Information processing device, arithmetic processing method, and electronic apparatus

An information processing device comprising:

• plural input registers including a first input register, a second input register, third input register, and a fourth input register;
• a first adding unit that performs addition processing for stored data of the first input register and stored data of the third input register;
• a second adding unit that performs addition processing for first connected data, which is obtained by connecting the stored data of the first input register as lower-order data and stored data of the second input register as higher-order data, and second connected data, which is obtained by connecting the stored data of the third input register as lower-order data and stored data of the fourth input register as higher-order data;
• and
• plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein
• in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers.

An arithmetic processing method for an information processing device including:

• plural input registers including a first input register and a second input register;
• an added value register;
• a first adding unit that performs addition processing using stored data of any one of the plural input registers;
• a second adding unit that performs addition processing using stored data of any one of the plural input registers;
• and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, the arithmetic processing method comprising:
• allocating the first input register and the second input register to the first adding unit out of the plural input registers;
• allowing the first adding unit to perform addition processing for stored data of the first input register and stored data of the second input register;
• allowing the second adding unit to perform addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register;
• and
• in each of given execution cycles, allowing the first adding unit to store a processing result of the first adding unit in any one of the plural output registers and the second adding unit to store a processing result of the second adding unit in any one of the plural output registers.