Vector multiplication processing device, and method and program thereof
OwnerTakashi Osadainventor
Life of this patent
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Abstract
Intended is to reduce power consumption without requiring shift of an operand. A vector multiplication processing device comprising a speed-up circuit (a fixed point overflow foresight circuit 5 and a sticky bit foresight circuit 6) to calculate a product of a first operand and a second operand input based on a multiplication instruction, which device comprises a multiplication circuit 4 (a partial product generation circuit 41 and a partial product control circuit 42) which uses the speed-up circuit and generates a partial product of the first operand and the second operand input to suppress circuit operation in a specific range resultingly not referred to related to generation of the partial product according to the multiplication instruction and a data format.
Claims13
A vector multiplication processing device which calculates a product of a first operand and a second operand input based on a multiplication instruction, comprising:
- an overflow foresight circuit of a fixed point data format;
- a sticky bit foresight circuit of a floating point data format;
- and
- a multiplication circuit including a partial product generation circuit which uses said overflow foresight circuit and said sticky bit foresight circuit to generate a partial product of a first operand and a second operand input and a partial product control circuit which suppresses operation of said partial product generation circuit in a specific region resultingly not referred to related to generation of said partial product according to said multiplication instruction and data format.
A vector multiplication processing method for use in a vector multiplication processing device including a multiplication circuit which calculates a product of a first operand and a second operand input based on a multiplication instruction, wherein said multiplication circuit includes
- a partial product generation step of generating a partial product of input first operand and second operand by using an overflow foresight circuit of a fixed point data format and a sticky bit foresight circuit of a floating point data format, and
- a circuit operation suppression step of suppressing circuit operation in a specific region resultingly not referred to related to generation of said partial product according to said multiplication instruction and data format.
A vector multiplication processing program of a vector multiplication processing device executed on a computer, which device comprises at least an overflow foresight circuit of a fixed point data format and a sticky bit foresight circuit of a floating point data format to calculate a product of a first operand and a second operand input based on a multiplication instruction, comprising:
- a partial product generation processing of generating a partial product of input first operand and second operand by using said overflow foresight circuit and sticky bit foresight circuit;
- and
- a circuit operation suppression processing of suppressing circuit operation in a specific region resultingly not referred to related to generation of said partial product according to said multiplication instruction and data format.
Dependencies are inferred from the claim text.