Cad flow for 15nm/22nm multiple fine grained wimpy gate lengths in sit gate flow

Abstract

Methods are described for forming an integrated circuit having multiple devices, such as transistors, with respective element lengths. The methods include a new CAD flow for producing masks used for exposing sidewall spacers which are to be etched to a smaller base width than other sidewall spacers and which in turn are used as an etch mask to form gate structures with smaller element lengths than those formed from the other sidewall spacers. Embodiments include generating a schematic of an integrated circuit and a corresponding netlist, establishing design rules for the integrated circuit, generating a computer aided design layout for the integrated circuit, plural transistors of the integrated circuit respectively having different gate lengths, checking the integrated circuit layout and netlist for compliance with the established design rules and for correspondence with the generated schematic, and generating a mask with different openings that correspond to the integrated circuit layout, in response to a satisfactory outcome of the checking step.

Dependencies are inferred from the claim text.