Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns

A method of manufacturing a semiconductor device, comprising:

• forming an underlying structure having contact regions on a substrate;
• forming an insulation layer on the substrate to cover the underlying structure;
• forming pads through the insulation layer, the pads being electrically connected to the contact regions;
• forming a mold layer on the insulation layer and the pads;
• forming an organic layer on the mold layer;
• forming a hard mask layer on the organic layer;
• forming a preliminary hard mask pattern having first openings by patterning the hard mask layer;
• forming a hard mask pattern having the first openings and second openings by patterning the preliminary hard mask pattern;
• forming width control spacers on sidewalls of the first and the second openings;
• forming an etching mask pattern by etching the organic layer using the hard mask pattern as an etching mask;
• forming a mold layer pattern having third openings by etching the mold layer using the etching mask pattern as an etching mask, the third openings exposing the pads;
• forming lower electrodes on bottoms and sidewalls of the third openings;
• forming a dielectric layer on the lower electrodes;
• and
• forming an upper electrode on the dielectric layer.

A method of manufacturing a semiconductor device, comprising:

• forming single crystalline pillars on a substrate;
• forming gate insulation layers on sidewalls of the single crystalline pillars;
• forming a gate electrode on the gate insulation layers to enclose the single crystalline pillars;
• forming an insulation layer on the gate electrode;
• forming impurity regions at upper portions of the single crystalline pillars;
• forming a mold layer on the insulation layer and the impurity regions;
• forming an organic layer on the mold layer;
• forming a hard mask layer on the organic layer;
• forming a preliminary hard mask pattern having first openings by patterning the hard mask layer;
• forming a hard mask pattern having the first openings and second openings by patterning the preliminary hard mask pattern;
• forming width control spacers on sidewalls of the first and the second openings;
• forming an etching mask pattern by etching the organic layer using the hard mask pattern as an etching mask;
• forming a mold layer pattern having third openings by etching the mold layer using the etching mask pattern as an etching mask, the third openings exposing the impurity regions;
• forming lower electrodes on bottoms and sidewalls of the third openings;
• forming a dielectric layer on the lower electrodes;
• and
• forming an upper electrode on the dielectric layer.