US 2010/0248424 A1 · Self-Aligned Chip Stacking

Abstract

A first semiconductor chip and a second semiconductor chip are provided with a matching pair of hydrophilic top surfaces each including a matched set of conductive contact structures. In one embodiment, the first semiconductor chip, the second semiconductor chip, or both is provided with a mesa of which the periphery coincides with the shape of a hydrophilic top surface. In another embodiment, the first semiconductor chip, the second semiconductor chip, or both is provided with a peripheral hydrophobic top surface that laterally surrounds a hydrophilic top surface. Prior to vertical stacking, a polar liquid coats the hydrophilic top surface of a first semiconductor chip. When a second semiconductor chip is placed on the polar liquid, the matching shapes of two hydrophilic surfaces are self-aligned by moving the second semiconductor chip as needed.

Claims20

Dependent claims

A method of forming a semiconductor structure comprising:

providing a first semiconductor chip including a mesa and a first recessed peripheral region around said mesa, wherein said mesa has a first hydrophilic top surface, and wherein a first periphery of said mesa has a first shape;
providing a second semiconductor chip having a second hydrophilic top surface, wherein a second periphery of said second hydrophilic top surface has a second shape, and wherein said second shape is a mirror image of said first shape;
applying a polar liquid to said first hydrophilic top surface, wherein an extent of said polar liquid is bounded by said first shape;
and
placing said second semiconductor chip on said polar liquid, wherein said polar liquid wets said second hydrophilic top surface, wherein said first periphery is self-aligned to said second periphery.

2 more elements

Dependencies are inferred from the claim text.

Self-Aligned Chip Stacking

Life of this patent

Self-Aligned Chip Stacking

Life of this patent

Abstract

Claims20