Clock change device and clock change method
AssigneeFujitsu Limited
InventorKatsuya TSUSHITA
Life of this patent
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Abstract
A clock change method includes: converting the serial data synchronized to a first clock into parallel data; latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock; and converting the latched parallel data into the serial data synchronized to the second clock, and wherein: each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a predetermined time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data.
Claims14
A clock change device comprising:
- a serial-parallel conversion unit which converts serial data synchronized to a first clock into parallel data;
- a data storing unit which latches the parallel data from the serial-parallel conversion unit with a latch timing that occurs once in every a number of clock cycles of a second clock;
- a parallel-serial conversion unit which converts the parallel data stored in the data storing unit into the serial data synchronized to the second clock;
- and
- a timing adjusting unit which, each time a packet of serial data synchronized to the first clock is received, performs a timing adjustment to adjust the latch timing so that the latch timing occurs a time after occurrence of a conversion timing of the serial-parallel conversion unit.
A clock change method comprising:
- converting serial data synchronized to a first clock into parallel data;
- latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock;
- and
- converting the latched parallel data into the serial data synchronized to the second clock, and wherein:
- each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data.
Dependencies are inferred from the claim text.