Asynchronous data recovery methods and apparatus

A data recovery apparatus comprising:

• a first oscillator adapted to receive a serial bit stream and to generate a first data detection signal based on the serial bit stream, wherein the first oscillator conveys oscillations in the first data detection signal during first time periods for which the serial bit stream conveys a relatively high voltage level;
• a second oscillator adapted to receive the serial bit stream and to generate a second data detection signal based on the serial bit stream, wherein the second oscillator conveys oscillations in the second data detection signal during second time periods for which the serial bit stream conveys a relatively low voltage level;
• edge detection circuitry operatively coupled with the first and second oscillators, wherein the edge detection circuitry is adapted to receive the first and second data detection signals, to detect transition edges within the first and second data detection signals, and to generate data storage signals that include first indications of detected transition edges in the first data detection signal and second indications of detected transition edges in the second data detection signal;
• and
• temporary storage operatively coupled with the edge detection circuitry, wherein the temporary storage includes a plurality of bit locations, and the temporary storage is adapted to receive the data storage signals, to write a logical 1 into a subset of the plurality of bit locations in response to receiving a first indication of a detected transition edge in the first data detection signal, and to write a logical 0 into the subset of the plurality of bit locations in response to receiving a second indication of a detected transition edge in the second data detection signal.

A method for asynchronously detecting data in a serial bit stream, the method comprising the steps of:

• generating a first data detection signal based on the serial bit stream, wherein the first data detection signal is generated to convey oscillations during first time periods for which the serial bit stream conveys a relatively high voltage level;
• generating a second data detection signal based on the serial bit stream, wherein the second data detection signal is generated to convey oscillations during second time periods for which the serial bit stream conveys a relatively low voltage level;
• generating first indications of detected transition edges in the first data detection signal and second indications of detected transition edges in the second data detection signal;
• writing a logical 1 into an unmasked bit location of a plurality of bit locations of a temporary storage in response to each of the first indications;
• and
• writing a logical 0 into the unmasked bit location of the plurality of bit locations in response to each of the second indications.