Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data

A data receiver comprising:

• a de-serializer that receives a serial data and a clock signal and converts the serial data into an M-bit receiver parallel data stream in synchronous with the clock signal;
• a receiver bit-sequence altering circuit that alters a sequence of bits in each word of the receiver parallel data stream by performing a first altering process including replacing specified ones of the bits in each word of the receiver parallel data stream with each other so that a bit-sequence restored parallel data stream is generated;
• a receiver cyclic pattern generating circuit that generates a reference cyclic pattern having a pattern length of N bits by using bits in the bit-sequence restored parallel data stream as initial values, where each of N and M is an integer larger than one and N and M are different with each other, the receiver cyclic pattern generating circuit further converts the reference cyclic pattern into an M-bit reference parallel data stream;
• an optional second bit-sequence altering circuit that alters a sequence of bits in each word of the reference parallel data stream by performing a second altering process opposite to the first altering process so that a bit-sequence altered reference parallel data stream is generated;
• and
• a comparing and checking circuit that compares one of (i) the receiver parallel data stream with the bit-sequence altered reference parallel data stream, and (ii) the bit-sequence restored parallel data stream with the reference parallel data stream.

A data transmitter comprising:

• a transmitter cyclic pattern generating circuit that generates a transmitter cyclic pattern having a pattern length of N bits and converts the transmitter cyclic pattern into an M-bit transmitter parallel data stream, where each of N and M is an integer larger than one and N and M are different with each other;
• a transmitter bit-sequence altering circuit that alters a sequence of bits in each word of the transmitter parallel data stream by performing a transmitter altering process including replacing specified ones of the bits in each word of the transmitter parallel data stream so that a bit-sequence altered transmitter parallel data stream is generated;
• and
• a serializer that converts the bit-sequence altered transmitter parallel data stream into a serial data in synchronous with a clock signal and transmits the serial data together with the clock signal.