Flexibly Integrating Endpoint Logic Into Varied Platforms
AssigneeIntel Corporation
InventorsMichael Klinglesmith, Mohan Nair, Joseph Murray
Life of this patent
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Abstract
In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
Claims22
An apparatus comprising:
- a virtual port coupled between an upstream fabric and an integrated device fabric, the virtual port including a master interface to interface with the upstream fabric and a target interface to interface with the integrated device fabric;
- the integrated device fabric including a multi-function logic to handle interrupts, power management messages, and non-function specific error messages, the integrated device fabric coupled to at least one intellectual property (IP) block and having a primary channel to communicate data and command information between the at least one IP block and the virtual port and a sideband channel to communicate sideband information between the at least one IP block and the multi-function logic;
- and
- the at least one IP block to perform a function, wherein the virtual port, the integrated device fabric and the IP block are adapted on a single semiconductor die.
A method comprising:
- receiving a message in an integrated device fabric from a virtual port coupled to the integrated device fabric, the integrated device fabric including a multi-function logic to handle first functionality for a plurality of endpoint devices, the integrated device fabric coupled to the plurality of endpoint devices and having a primary channel to communicate data and command information between the plurality of endpoint devices and the virtual port and a sideband channel to communicate sideband information between the plurality of endpoint devices and the multi-function logic;
- broadcasting a command portion of the message to the plurality of endpoint devices coupled to the integrated device fabric via the primary channel;
- receiving a decode confirmation from a targeted one of the plurality of endpoint devices to indicate that the message is intended for the targeted endpoint device;
- and
- determining whether the targeted endpoint device has available resources to handle the message and if so sending the message to the targeted endpoint device.
A system comprising:
- a processor;
- a root complex fabric coupled to the processor, a plurality of integrated endpoint devices and a root port, the root port coupled to a Peripheral Component Interconnect Express (PCIe) device via an off-chip link, wherein the PCIe device is visible to software executing on the processor, the root port and the PCIe device each including a transaction layer, a link layer and a physical layer;
- a virtual root port coupled to the root complex fabric and having a master interface to interface with the root complex fabric and a target interface to interface with an integrated device fabric;
- and
- the integrated device fabric coupled to the virtual root port via an on-chip link and including a multi-function logic to handle interrupts, power management messages, and non-function specific error messages, the integrated device fabric coupled to at least one agent and having a primary channel to communicate data and command information between the at least one agent and the virtual root port and a sideband channel to communicate sideband information between the at least one agent and the multi-function logic, wherein communication between the virtual root port and the at least one IP block is at the transaction layer without intervention of the link layer or the physical layer and the at least one agent is visible to the software executing on the processor as a PCIe device coupled to the virtual root port via an off-chip link.
Dependencies are inferred from the claim text.