Clock generators, memory circuits, systems, and methods for providing an internal clock signal

An memory circuit comprising:

• at least one memory array for storing data;
• and
• a control circuit, the control circuit being capable of providing at least one signal for accessing the data of the memory array, the clock generator comprising:
• a first input end, the first input end capable of receiving a first clock signal including a first state transition and a second state transition, a first pulse width being defined by the first state transition and the second state transition;
• a second input end, the second input end capable of receiving a second clock signal having a third state transition, a time period being defined by the first state transition and the third state transition;
• and
• an output end configured to output a third clock signal having a second pulse width defined by a fourth state transition and a fifth state transition of the third clock signal, wherein the fifth state transition of the third clock signal is triggered by the second state transition of the first clock signal if the first pulse width is larger than the time period, or by the third state transition of the second clock signal if the first pulse width is not larger than the time period.

A method for generating an internal clock signal, the method comprising:

• receiving an external clock signal including a first state transition and a second state transition, the external clock signal having a first pulse width ranging from the first state transition and the second state transition;
• receiving a clock reset signal including a third state transition, the clock reset signal having a time period ranging from the first state transition to the third state transition;
• comparing the first pulse width and the time period;
• and
• outputting the internal clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition, wherein the fifth state transition of the internal clock signal is capable of being triggered by the second state transition of the external clock signal or the third state transition of the reset clock signal depending on the comparison of the first pulse width and the time period.