Address converting circuit and semiconductor memory device using the same

A semiconductor memory, comprising:

• an address converting circuit which buffers an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group;
• a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group;
• and
• a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group.

A semiconductor memory device, comprising:

• an address latch unit which buffers an address and a bank signal and generates a latch bank signal and a latch address for activating a data access path;
• a variable address generation unit which converts the latch address and generates a variable address for activating a data access path in response to the latch bank signal;
• a first column decoder which decodes the variable address and generates a first output enable signal;
• a second column decoder which decodes the latch address and generates a second output enable signal;
• a first bank group inputting or outputting data through a data access path activated by the first output enable signal;
• and
• a second bank group inputting or outputting data through a data access path activated by the second output enable signal.