Semiconductor memory

Abstract

An SRAM module includes bit cells arranged within an SRAM array of N×M, and a replica SRAM cell array of a replica bit cell used for bit cell performance measurement, and can control the number of replica bit cells used for performance measurement. When the clock generator circuit generates an internal pulse upon receiving a clock, the clock generator circuit generates a leading edge of a pulse by a clock (clk), and generates a trailing edge thereof by a delay circuit including the delay of the replica bit cells. The internal pulse is used for controlling the activation time of the word lines for selecting the memory cell, and the timing of a bit line control circuit (a bit line precharger circuit, an address logic circuit, and a sense amplifier circuit).

Dependencies are inferred from the claim text.