Semiconductor memory device and refresh control method

A semiconductor memory device comprising:

• a command decoder that recognizes an externally supplied refresh command and outputs a refresh instruction signal;
• and
• a refresh command generating circuit that outputs an internal refresh signal in response to the refresh instruction signal, the refresh command generating circuit comprising a refresh number control circuit that controls the number of times that the internal refresh signal is output in response to one refresh instruction signal,
• wherein the number of times that the internal refresh signal is output in response to one refresh instruction signal is equal to the number of refresh operations in the case in which each of a plurality of banks is refreshed and, after a refresh address counter value designating a word line has been changed, a part of the plurality of banks, the number of the part of the plurality of banks being greater than or equal to one and less than the number of the plurality of banks, is further refreshed.

A semiconductor memory device comprising:

• a command decoder that recognizes an externally supplied refresh command and outputs a refresh instruction signal;
• and
• a refresh command generating circuit that outputs an internal refresh signal in response to the refresh instruction signal, the refresh command generating circuit comprising a refresh number control circuit that controls the number of times that the internal refresh signal is output,
• wherein the number of times that the internal refresh signal is output is equal to the number of refresh operations in the case in which, in response to one refresh instruction signal, each of a plurality of banks is refreshed and, after a refresh address counter value designating a word line has been changed, a part of the plurality of banks, the number of the part of the plurality of banks being greater than or equal to one and less than the number of the plurality of banks, is further refreshed, and
• the refresh number control circuit comprises:
• a refresh number counter circuit that measures the number of times that the internal refresh signal is output;
• and
• a comparison unit that determines whether or not the refresh number counter circuit counts up in response to receipt of the internal refresh signal, by the comparison with number-of-times information that has been determined in advance.