Semiconductor memory devices including burn-in test circuits
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Hyun Choi, Sang-Seok Kang
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Abstract
A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.
Claims20
An integrated circuit memory device, comprising:
- a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell;
- and
- a controller circuit configured to provide first and second precharge voltages to the first and second bitlines, respectively,
- wherein the first precharge voltage comprises a positive power supply voltage and the second precharge voltage comprises a negative stress voltage during a burn-in test mode of operation.
An integrated circuit memory device, comprising:
- a memory cell array comprising a first and second memory cells having a leakage current path therebetween;
- first and second bit lines coupled to the first and second memory cells, respectively;
- and
- a controller circuit coupled to the first and second bit lines and operable to provide first and second precharge voltages to the first and second bitlines, respectively,
- wherein, during a burn-in test mode of operation, the controller is operable to provide the first and second precharge voltages such that a difference between the first and second precharge voltages is sufficient to remove the leakage current path between the first and second memory cells.
Dependencies are inferred from the claim text.