Semiconductor storage device and redundancy method
AssigneeKabushiki Kaisha Toshiba
InventorsTakayuki IWAI, Mariko IIZUKA
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Abstract
A semiconductor storage device includes a normal area that contains a plurality of memory cells and a redundancy area that contains a plurality of memory cells. The semiconductor storage device further includes a delaying unit that changes, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.
Claims10
A semiconductor storage device that includes a normal area having a plurality of memory cells incorporated therein and a redundancy area having a plurality of memory cells incorporated therein, the semiconductor storage device comprising:
- a delaying unit that changes, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.
A redundancy method implemented by a semiconductor storage device that includes a normal area having a plurality of memory cells incorporated therein and a redundancy area having a plurality of memory cells incorporated therein, the redundancy method comprising:
- changing, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.
Dependencies are inferred from the claim text.