Integrated circuit memory having assisted access and method therefor

A method for accessing a memory array comprising:

• implementing redundancy in the memory array to substitute a redundant memory cell for a failed memory cell;
• testing, using a first test, the memory array to determine a lowest power supply voltage at which all memory cells of the memory array will operate;
• determining a weak memory cell of the memory array;
• substituting a redundant memory cell for the weak memory cell;
• designating the weak memory cell to be only a test cell;
• supplying the memory array with a first power supply voltage;
• receiving a request for a change of the first power supply voltage to a second power supply voltage;
• in response to receiving the request, testing, using a second test, the test cell to determine if both read and write operations can be performed correctly on the test cell at the second power supply voltage,
• if the test cell passes the second test, accessing the memory array at the second power supply voltage, and
• if the test cell fails the second test, providing a third power supply voltage to the test cell and testing the test cell using a third test to determine if the test cell will function correctly at the third power supply voltage;
• and
• if the test cell passes the third test, accessing the memory array at the third power supply voltage.

An integrated circuit comprising:

• a memory array comprising a plurality of memory cells organized in rows and columns, wherein a memory cell of the plurality of memory cells is designated as a test memory cell;
• a plurality of redundant memory cells for implementing redundancy in the memory array, wherein a redundant memory cell of the plurality of redundant memory cells is used to substitute for the test memory cell during operation of the integrated circuit;
• an error detection circuit, coupled to the memory array, for detecting a failure of the test memory cell concurrently with an access to a memory cell of the plurality of memory cells;
• and
• a voltage control circuit, coupled to the memory array and to the error detection circuit, for changing activating an access assist operation in response to the error detection circuit detecting a failure of the test memory cell.