System and method for delay locked loop relock mode

A system comprising:

• a memory device comprising:
• a delay locked loop (DLL) circuit comprising:
• a delay line to receive an input clock signal and to generate an output clock signal;
• and
• a feedback circuit coupled to the delay line, wherein the feedback circuit is to adjust a delay interval to align the clock phase of the output clock signal to the clock phase of the input clock signal, and wherein the delay interval is to be locked onto the delay line;
• and
• a memory controller coupled to the DLL circuit, wherein the memory controller is to switch off the feedback circuit after the delay interval is locked onto the delay line, and wherein the memory controller is to periodically switch on the feedback circuit based on the locked delay interval to re-align the clock phase of the output clock signal to the clock phase of the input clock signal.

A method of controlling a memory device, comprising:

• adjusting a delay interval by a feedback circuit to align a clock phase of an output clock signal to a clock phase of an input clock signal, wherein the feedback circuit is coupled to a delay line and the delay line receives the input clock signal and generates the output clock signal;
• locking the delay interval on the delay line;
• powering down the feedback circuit after locking the delay interval;
• and
• powering up the feedback circuit in periodic intervals to align the clock phase of the output clock signal to the clock phase of the input clock signal using the delay interval locked on the delay line.