Tracking Circuit for Reducing Faults in a Memory

An integrated circuit including at least one embedded memory circuit, the embedded memory circuit comprising:

• a plurality of memory cells;
• a plurality of bit lines and row lines connected to the memory cells for accessing selected ones of the memory cells;
• a programmable voltage source adapted for connection to at least one of the bit lines and operative to charge the at least one bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the at least one bit line;
• a control circuit coupled to the at least one bit line and operative to oppose discharge of the at least one bit line during at least a portion of a given memory read cycle;
• and
• a tracking circuit connected to the control circuit and operative to control at least one of (i) a delay in activation of the control circuit and (ii) a duration of time the control circuit is active as a function of at least one parameter affecting a signal development time of a data signal on the at least one bit line, the data signal being indicative of data stored in the selected one of the memory cells over at least one of process, voltage and temperature variations to which the embedded memory circuit is subjected.

An electronic system, comprising:

• at least one integrated circuit including at least one memory circuit, the memory circuit comprising:
• a plurality of memory cells;
• a plurality of bit lines and row lines connected to the memory cells for accessing selected ones of the memory cells;
• a programmable voltage source adapted for connection to at least one of the bit lines and operative to charge the at least one bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the at least one bit line;
• a control circuit coupled to the at least one bit line and operative to oppose discharge of the at least one bit line during at least a portion of a given memory read cycle;
• and
• a tracking circuit connected to the control circuit and operative to control at least one of (i) a delay in activation of the control circuit and (ii) a duration of time the control circuit is active as a function of at least one parameter affecting a signal development time of a data signal on the at least one bit line, the data signal being indicative of data stored in the selected one of the memory cells over at least one of process, voltage and temperature variations to which the memory circuit is subjected.

A method for reducing faults in a memory circuit during at least a portion of a given memory cycle, the memory circuit including a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for selectively accessing the memory cells, the method comprising the steps of:

• precharging at least one of the bit lines to a prescribed voltage level;
• accessing a selected one of the memory cells in the memory circuit corresponding to the at least one bit line during at least a portion of a memory read cycle;
• maintaining the at least one bit line substantially at the prescribed voltage level by opposing discharge of the at least one bit line during at least a portion of the memory read cycle;
• and
• controlling a delay in activation of a control circuit operative to maintain the at least one bit line at substantially the prescribed voltage level and controlling a duration of time the control circuit is active as a function of at least one parameter affecting a signal development time of a data signal on the at least one bit line, the data signal being indicative of data stored in the selected one of the memory cells over at least one of process, voltage and temperature variations to which the memory circuit is subjected.

A semiconductor structure, comprising:

• a first integrated circuit die;
• and
• at least a second integrated circuit die mechanically mounted proximate to and electrically interconnected with the first integrated circuit die, at least one of the first and at least second integrated circuit die including a memory circuit comprising:
• a plurality of memory cells;
• a plurality of bit lines and row lines connected to the memory cells for accessing selected ones of the memory cells;
• a programmable voltage source adapted for connection to at least one of the bit lines and operative to charge the at least one bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the at least one bit line;
• a control circuit coupled to the at least one bit line and operative to oppose discharge of the at least one bit line during at least a portion of a given memory read cycle;
• and
• a tracking circuit connected to the control circuit and operative to control at least one of (i) a delay in activation of the control circuit and (ii) a duration of time the control circuit is active as a function of at least one parameter affecting a signal development time of a data signal on the at least one bit line, the data signal being indicative of data stored in the selected one of the memory cells over at least one of process, voltage and temperature variations to which the memory circuit is subjected.