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US 2010/0246292 A1Published application
Cell Inferiority test circuit
AssigneeHynix Semiconductor Inc.
InventorJoo Hyeon Lee
Life of this patent
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Abstract
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.
Claims17
A cell inferiority test circuit, comprising:
- a compression data generator configured to compress selected data in response to selection signal and to generate compression data including information about cell inferiority;
- a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal;
- and
- an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.
1 more element
A cell inferiority test circuit, comprising:
- a first strobe signal delay circuit configured to delay a strobe signal for a first delay period in response to a first test signal;
- a second strobe signal delay circuit configured to delay an output signal of the first strobe signal delay circuit for a second delay period, in response to a second test signal, and to output a delayed strobe signal;
- and
- an input/output line driver configured to receive compression data in sync with the delayed strobe signal and to drive a global input/output line.
1 more element
Dependencies are inferred from the claim text.