Method and apparatus for determining write leveling delay for memory interfaces

A method for determining write leveling delay for a plurality of memory devices having command signal lines connected in series to each memory device, comprising the operations of:

• determining a device delay value for each memory device, each device delay value indicating a period of time to delay a control signal that is unique to an associated memory device when accessing a related memory device;
• comparing a first device delay value associated with a first memory device to a second device delay value associated with a second memory device, the second memory device connected in series after the first memory device;
• and
• setting the first device delay value to a lower value when the first delay value is greater than the second device delay value.

A memory controller capable of performing write leveling operations, comprising:

• a plurality of control lines, each capable of being configured to access a memory device via a control signal;
• a plurality of command signal lines capable of being placed in serial communication with each memory device;
• logic that determines a device delay value for each memory device, wherein each device delay value indicates a period of time to delay a control signal that is unique to an associated memory device when accessing the associated memory device;
• and
• logic that sets a prior device delay value to a lower value when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.