Methods, devices, and systems relating to a memory cell having a floating body

A method of forming a memory cell, comprising:

• forming a passage through an insulation layer overlying a silicon layer;
• forming another layer comprising silicon over the insulation layer, into the passage, and in contact with the silicon layer;
• forming a plurality of trenches through the another layer, the insulation layer, and the silicon layer, wherein the passage is positioned between the plurality of trenches;
• forming a dielectric layer adjacent each outer vertical surface of the silicon layer adjacent a trench of the plurality of trenches and extending from a top surface of the silicon layer to a bottom surface of the silicon layer;
• depositing a conductive material at least partially within each trench of the plurality to at least a depth above a top surface of the silicon layer;
• and
• forming a transistor over the insulation layer, wherein a drain region and a source region of the transistor overlie and are adjacent to the insulation layer with the another layer positioned therebetween.

A memory device, comprising:

• a memory array including a plurality of memory cells, each memory cell comprising:
• a transistor overlying an insulation layer and comprising a drain region and a source region adjacent the insulation layer;
• a floating body having a first region adjacent the drain region and the source region, a second region distant from the first region, and a passage extending through the insulation layer and coupling the first region to the second region;
• and
• a bias gate at least partially surrounding the second region and configured to be operably coupled to a bias voltage;
• wherein each outer vertical surface of the second region comprises a dielectric layer formed adjacent thereto and positioned between a vertical surface of the second region and the bias gate.

An electronic system, comprising:

• at least one processor;
• and
• at least one memory device including a plurality of memory cells, each memory cell comprising:
• a transistor having a drain region and a source region overlying and adjacent to an insulation layer;
• a first region overlying the insulation layer and positioned between the source region and the drain region;
• a second region comprising silicon and remotely positioned from the first region;
• a passage extending from the first region through the insulation layer to the second region;
• a bias gate at least partially surrounding the second region and adapted for operable coupling to a bias voltage;
• and
• a dielectric layer positioned adjacent each outer vertical surface of the second region and extending from a top surface of the second region to a bottom surface of the second region.