Accessing data within a memory formed of memory banks

A memory comprising:

• a plurality of data storage cells for storing individual units of data, said plurality of data storage cells being arranged in an array;
• a plurality of said arrays;
• each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry;
• delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay circuitry comprises an initial delay element for providing a first delay to said control signal sent to all of said arrays and further delay elements for providing further delays to said control signal sent to at least some of said arrays, a length of said further delays being inversely dependent on a time taken for an input data access signal to reach an array and an output data signal to reach an output of said memory from said array.