Semiconductor memory device having bit line pre-charge unit separated from data register
AssigneeMicron Technology, Inc.
InventorSHIGEKAZU YAMADA
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Abstract
A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row decoder, and a column decoder. The memory cell array includes a pre-charge unit that is placed between a plurality of memory cell arrays. The pre-charge unit pre-charges a bit line in a read operation. A data register is separated from the pre-charge unit and is located away from the arrays. Write data are coupled from a data register to the arrays, and read data are coupled from the arrays to the data register.
Claims1
A memory device, comprising:
- a memory cell array comprising a plurality of memory cells and bit lines to which the memory cells are coupled;
- a pre-charge unit placed adjacent the memory cell array, the pre-charge unit being operable to pre-charge at least some of the bit lines in the memory cell arrays;
- and
- a data register coupled to the bit lines in the memory cell array, the data register being positioned a distance from the memory cell array that is substantially greater than the distance between the pre-charge unit and the memory cell array.
Dependencies are inferred from the claim text.