Charge loss compensation during programming of a memory device

A method for quick charge loss compensation in a non-volatile memory device, the method comprising:

• programming, at a first programming rate, a selected memory cell;
• inhibiting programming of the selected memory cell in response to the selected memory cell passing a first program verify operation;
• performing a second program verify operation on the selected memory cell after the first program verify operation;
• and
• programming the selected memory cell at a second programming rate in response to failing the second program verify operation.

A method for programming a NAND flash memory device, the method comprising:

• applying a plurality of programming pulses to a control gate of a selected memory cell, each programming pulse having an associated program verify operation and the plurality of programming pulses starting at a minimum programming voltage and increasing by a step voltage over a preceding programming pulse;
• inhibiting programming of the selected memory cell after the selected memory cell passes a first program verify operation;
• applying at least one programming pulse to the control gate of the selected memory cell while the selected memory cell is inhibited;
• performing a second program verify operation on the selected memory cell;
• if the second program verify operation fails, applying a final programming pulse to the control gate of the selected memory cell while applying the step voltage to a drain of the selected memory cell;
• and
• locking the selected memory cell from further programming.