Erase cycle counter usage in a memory device
AssigneeMicron Technology, Inc.
InventorsViolante Moschiano, Giovanni Santin, Luca De Santis
Life of this patent
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Abstract
Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
Claims25
A method of operating a memory device, comprising:
- maintaining an erase cycle counter value for each memory block of a plurality of memory blocks of the memory device where each memory block comprises a plurality of memory cells;
- storing each erase cycle counter value in a corresponding memory block;
- and
- adjusting a programming voltage applied to one or more memory cells of a particular block of memory cells in response to the erase cycle counter value corresponding to the particular block.
A method of operating a memory device, comprising:
- selecting a memory block of the memory device for erasure where the selected memory block is selected from a plurality of memory blocks each memory block comprising one or more memory cells;
- performing a read operation of an erase cycle counter value corresponding to the selected memory block;
- storing the read erase cycle counter value in the memory device in a location other than the selected memory block;
- performing an erase operation on the selected memory block;
- updating the read erase cycle counter value in response to the erase operation performed on the selected memory block;
- storing the updated erase cycle counter value corresponding to the selected memory block in the memory device;
- and
- determining an initial programming voltage to apply to one or more memory cells of the selected memory block where the initial programming voltage is determined in response to the erase cycle counter value corresponding to the selected memory block.
A memory device, comprising:
- a plurality of memory cells arranged in a plurality of erase blocks each erase block storing an erase cycle counter value representative of a number of erase cycles performed on that erase block;
- and
- control circuitry, wherein the control circuitry is configured to determine an initial programming voltage to apply to memory cells of a selected erase block, update the erase cycle counter value for the selected erase block in response to an erase operation performed on the selected erase block and store the updated erase cycle counter value in the selected erase block;
- and
- wherein the determined initial programming voltage is based upon the erase cycle counter value stored in the selected erase block.
A electronic system, comprising:
- a host device;
- and
- a memory device coupled to the host, the memory device comprising:
- an array of memory cells arranged in a plurality of erase blocks each erase block storing an erase cycle counter value representative of a number of erase cycles performed on that erase block;
- and
- control circuitry, wherein the control circuitry is configured to read an erase cycle counter value stored in a selected erase block of the plurality of erase blocks, determine an initial programming voltage to apply to memory cells of the selected erase block where the initial programming voltage is determined based upon the erase cycle counter value read from the selected erase block, update the erase cycle counter value in response to an erase operation performed on the selected erase block and store the updated erase cycle counter value in the selected erase block.
Dependencies are inferred from the claim text.